Configuration Details
ShadowFI employes a dictionary structure to allocate all the project configurations across the whole execution pipeline.
shadowfi_root:
project:
name:
root_proj_dir:
bench_name:
work_dir:
proj_config_file:
design_config:
design_root_dir:
inc_directories: #<optional list>
-
src_path:
src_list_files: #<optional list>
-
top_module:
module_params: #<optional list>
-
testbench_config:
external_tb_build: False
external_tb_config:
tb_build_cmd: #<optional list>
-
tb_working_dir:
internal_tb_config:
tb_list_files:
-
tb_path:
tb_working_dir:
tb_target_file:
tb_top:
tb_inc_directories: #<optional list>
-
tb_params: #<optional list>-
-
tb_verilator_params: #<optional>
sim_config:
tasks: 1
engines: 1
sim_runtime:
max_num_faults: 1
work_sim_root_dir:
work_sim_dir:
tb_build_dir:
tb_run_info:
tb_run_script:
tb_run_args: #<optional str>
tb_run_timeout: #<optional>
tb_run_env_vars: #<optional list>
tb_sdc_check_info:
tb_sdc_check_script:
tb_sdc_check_args: #<optional>
tb_sdc_check_env_vars: #<optional list>
tb_test_app_info:
test_app: #<optional>
test_app_args: #<optional>
test_app_env_vars: #<optional list>
test_app_dirs: #<list rel dirs>
test_app_files: #<list rel files>
sbtr_config:
sbtr_dir:
mode:
component_selection:
hierarchical_component:
-
target_modules:
-
fault_model: S@
max_num_faults: -1
emu_config:
work_dir_client: ~/work
engines: 1
target_nodes:
- 1
design_name: TCU_1_SBTR
fpga_engine_module: ./benchmarks/HyperFPGA/1_TCU/hyperfpga/fpga_engine.py
load_args:
work_dir: ./
write_args:
work_dir: ./
mode: golden
max_num_faults: 1
sim_runtime: 10000
tasks: 2
src_data_root_dir: ./benchmarks/Cores/TCU/TCU_2/tb
test_data_info:
test_app_dirs:
test_app_files:
- ./values_dot_product.csv
fpga_hw:
vivado_proj_dir: ./benchmarks/HyperFPGA/1_TCU/vivado/1_SBTR/hyperfpga-basic-test-3be11
Basic Project Settings
The project configuration holds the main information related to the project, including working directories, project name, etc.
shadowfi_root: #path to the shadowfi root directory
project:
name: # name of the project (e.g., CUT)
root_proj_dir: #path to the directory where the projects are handled (e.g., /home/user/shadowfi/projects/CUT )
bench_name: #An arbitrary name for the evalaution benchmark (e.g., BENCH-CUT)
work_dir: #Work directory for the project (e.g., /home/user/shadowfi/projects/CUT/work)
proj_config_file: #the full path to the configuration file of the project (e.g., /home/user/shadowfi/projects/CUT/config.yaml)
Design Information Settings
design_config:
design_root_dir: # Path to the directory where the target design is alocated (e.g., /home/user/shadowfi/benchmarks/Cores/TCU/TCU_2)
inc_directories: #Optional list of include directories
- #dir1 (e.g., benchmarks/Cores/TCU/TCU_2/src)
- #dir2 ...
src_path: # path to source directory (e.g., benchmarks/Cores/TCU/TCU_2/src)
src_list_files: #<optional list of verilog files>
- #file1.v (e.g., benchmarks/Cores/TCU/TCU_2/src/TCU_core.v )
- #file2.v ...
top_module: #name of the top module (e.g., sub_tensor_core)
module_params: #<optional list>
- #param1 (e.g., M=10)
- #param2 (e.g., NAME="HELLO")
- #...
Saboteur Insertion Settings
sbtr_config:
sbtr_dir: #directory where the saboteur infrastructure of the design will be generated (e.g., /home/user/shadowfi/projects/CUT/sbtr)
mode: #type of component selection [top,random, hierarchy]
component_selection: # selection of the components whitin the CUT targeted for saboteur insertion when using mode=hierarchy
hierarchical_component: #list of component paths and their linked sabotaged components
- #target instance -> sabotaged component (e.g., d_unit0@adder0->fpadd_3_pipe_sbtr)
- #target instance -> sabotaged component (e.g., d_unit1@adder0->fpadd_3_pipe_sbtr)
- #target instance -> sabotaged component (e.g., d_unit2@adder0->fpadd_3_pipe_sbtr)
target_modules: #list of HDL design modules to be extracted
- #name of the original module (e.g., fpadd_3_pipe )
fault_model: # fault modeld defintion (e.g., S@)
max_num_faults: #set the number maximum of fault to be inserted with saboteurs (e.g., -1 means all nets intrumented)
TestBench Settings For Simulation Workflows
testbench_config:
external_tb_build: False
external_tb_config:
tb_build_cmd: #<optional list>
-
tb_working_dir:
internal_tb_config:
tb_list_files:
-
tb_path:
tb_working_dir:
tb_target_file:
tb_top:
tb_inc_directories: #<optional list>
-
tb_params: #<optional list>-
-
tb_verilator_params: #<optional>
Fault Simulation Settings For Simulation Workflows
sim_config:
tasks: #Numbr of simulations used to split the full fault injection campaign (e.g., 128)
engines: #NUmber of parallel processors/nodes
sim_runtime: #Duration of the simulation in clock cycles (e.g., 200000), this depend of the target CUT design
max_num_faults: # Number of faults to be simulated. This parameter is different from the number of faults intrumented.
work_sim_root_dir: #Path to the root simulation directory in the original design testbench
work_sim_dir: #Path to the simulation directory in the original design testbench relative to work_sim_root_dir, this can be the same as work_sim_root_dir
tb_build_dir: #Path to the directory where verilatorswas compiled, relative to work_sim_root_dir (e.g., ./obj_dir )
tb_run_info:
tb_run_script: #path to the "run.sh" script (e.g., ./run.sh)
tb_run_args: #<optional str>
tb_run_timeout: #<optional>
tb_run_env_vars: #<optional list>
-
tb_sdc_check_info:
tb_sdc_check_script: #path to the "run.sh" script (e.g., ./sdc_check.sh)
tb_sdc_check_args: #<optional>
tb_sdc_check_env_vars: #<optional list>
-
tb_test_app_info:
test_app: #<optional>
test_app_args: #<optional>
test_app_env_vars: #<optional list>
-
test_app_dirs: #<list rel dirs>
-
test_app_files: #<list rel files>
-
FPGA Emulation Settings For Fault Emulation Workflow
emu_config:
work_dir_client: # FPGA-SOC client working directory (e.g., ~/work)
engines: # Number of FPGA engines to be used (e.g., 16)
target_nodes: # selection of the specific nodes
- #node 1 (e.g., 1)
- #node 1 (e.g., 1)
- ...
- - #node 16 (e.g., 16)
design_name: # FPGA design name (e.g., TCU_1_SBTR)
fpga_engine_module: # FPGA engine configuration for specific CUU (e.g., ./benchmarks/HyperFPGA/1_TCU/hyperfpga/fpga_engine.py)
load_args: # load arguments
work_dir: # workign directory (e.g., ./)
write_args:
work_dir: # workign directory (e.g., ./)
mode: #dafault model (e.g., golden)
max_num_faults: #Max number of faults to be evalauted (e.g., -1 meaning all intrumented ones)
sim_runtime: # Timeot (e.g, 10000 seconds)
tasks: # number of paralel tasks to be executed (e.g., 2)
src_data_root_dir: # path to the root directory where test-data and other necesary scripts are allocated (e.g., ./benchmarks/Cores/TCU/TCU_2/tb)
test_data_info:
test_app_dirs: # list of directories, relative to src_data_root_dir, required to be copied to all computing nodes
-
test_app_files: # list of files, relative to src_data_root_dir, required to be copied to all computing nodes
- #file 1 (e.g., ./values_dot_product.csv)
fpga_hw:
vivado_proj_dir: #path to the vivado project ready to generate FPGA bitstreams (e.g., ./benchmarks/HyperFPGA/1_TCU/vivado/1_SBTR/hyperfpga-basic-test-3be11)